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? semiconductor components industries, llc, 2016 january, 2016 ? rev. 4 1 publication order number: ncp1565/d ncp1565 highly integrated dual-mode active clamp pwm controller the ncp1565 is a highly integrated dual?mode active?clamp pwm controller targeting next?generation high?density, high?performance and small to medium power level isolated dc?dc converters for use in telecom and datacom industries. it can be configured in either voltage mode control with input voltage feed?forward or peak current mode control. peak current mode control may be implemented with input voltage feed forward as well. adjustable adaptive overlap time optimizes system efficiency based on input voltage and load conditions. this controller integrates all the necessary control and protection functions to implement an isolated active clamp forward or asymmetric half?bridge converter. it integrates a high?voltage startup bias regulator. the ncp1565 has a line undervoltage detector, cycle?by?cycle current limiting, line voltage dependent maximum duty ratio limit, and programmable overtemperature protection using an external thermistor. it also includes a dual?function flt/sd pin used for communicating the presence of a fault but also for shutting down the controller. general features ? support voltage mode control and peak current mode control ? line feedforward ? adaptive overlap time control for improved efficiency ? integrated 120 v high voltage startup circuit ? programmable line undervoltage lockout (uvlo) with adjustable hysteresis ? cycle by cycle peak current limiting ? overcurrent protection based on average current ? short circuit protection ? programmable duty ratio clamp ? programmable soft?start ? programmable shutdown and restart delays ? programmable external overtemperature protection using thermistor ? flt/sd pin used for fault reporting and shutdown input ? programmable oscillator with 1.5 mhz maximum frequency ? 5 v/2% voltage reference ? main switch drive capability of ?2 a/3 a ? active clamp switch drive capability of ?2 a/1 a ? v cc range: from 6.5 v to 20 v ? these devices are pb?free, halogen free/bfr free and rohs compliant typical applications ? high efficiency isolated dc?dc converters ? server power supplies ? 24 v and 48 v telecom systems ? 42 v automotive applications www. onsemi.com marking diagram qfn24 mn suffix case 485cw see detailed ordering, marking and shipping information on page 30 of this data sheet. ordering information a = assembly location l = wafer lot y = year w = work week = pb?free package 1565 alyw 1 (note: microdot may be in either location) vsclamp nc vin nc nc uvlo otp ref cs nc res comp ramp ss dlmt dt rt agnd refa outa pgnd outm vcc flt/sd 1 2 3 4 5 6 18 17 16 15 14 13 789101112 24 23 22 21 20 19 pin connections
ncp1565 www. onsemi.com 2 figure 1. typical application circuit in voltage mode control
ncp1565 www. onsemi.com 3 figure 2. typical application circuit in current mode control
ncp1565 www. onsemi.com 4 figure 3. functional block diagram
ncp1565 www. onsemi.com 5 detailed pin description pin number name function 1 ramp pwm modulator ramp. in voltage mode an external r?c circuit from v in sets the pwm ramp slope to implement feedforward. in current mode control, the resistor of the external r?c circuit connects to ref for ramp compensation. 2 ss soft?start control. a 20 a current source charges the external capacitor connected to this pin. duty ratio is limited during startup by comparing the voltage on this pin to a level?shifted vsclamp signal. under steady state conditions, the ss voltage is approximately 4.5 v. once a fault is detected the ss capacitor is discharged and the controller is disabled. 3 dlmt maximum duty ratio limit. a resistor between this pin and agnd sets the maximum duty ratio of the controller. 4 dt dead time control. an external resistor between this pin and agnd sets the overlap time delay between outm and outa. 5 rt oscillator frequency setting pin. the total external resistance connected between the rt and agnd pins sets the internal oscillator frequency. 6 agnd analog circuit ground reference. all control and timing components that connect to agnd should have the shortest loop possible to this pin to improve noise immunity. it should be tied to pgnd at the return of the power stage. 7 comp input to the pulse width modulator. an external optocoupler connected between the ref and comp pin sources current into an internal npn current mirror. the maximum duty ratio is achieved when no current is sourced by the optocoupler. the duty cycle reduces to zero once the source current exceeds 850 a. the internal current mirror improves the frequency response by reducing the ac voltage across the optocoupler transistor. 8 res restart time control. a capacitor between this pin and agnd set the shutdown delay and hiccup mode restart delay time. if a restart fault is detected, a pull?up current source, i res(src1) , typically 20 a is enabled. if the res pin voltage, v res , exceeds the restart threshold, v res(th) , typically 1 v, the controller enters restart mode. i res(src1) is disabled once in restart mode and a second pull up current source, i res(src2) , typically 5 a enabled. i res(src2) is disabled once v res reaches v res(peak) , typically 4 v. a pull?down current source, i res(snk) , typically 5 a, is enabled until vres falls below v res(valley) typically 2 v. the controller restarts after 32 v res charge/discharge cycles. 9 nc no connect. 10 cs current sense input. the current sense signal is used for current?mode control, adaptive dead time control, cycle?by?cycle current limiting, over?current protection and short circuit protection, etc. if the cs voltage exceeds the cycle by cycle current limit threshold, v ilim , typically 0.45 v, the drive pulse is terminated. internal leading edge blanking prevents triggering of the cycle by cycle current limit during normal operation. a short circuit condition exists if v cs exceeds the short?circuit threshold, v ilim(sc) , typically set to 0.7 v, during two consecutive clock pulses. 11 ref precision 5 v reference. maximum output current is 12 ma. it is required to bypass the reference with a capacitor. the recommended capacitance ranges between 0.1 to 0.47 f. 12 otp over?temperature protection. a voltage divider containing a ntc connects to this pin. 13 vcc positive input supply. this pin connects to an external capacitor for energy storage. an internal current source, i start , supplies current from v in to this pin. once v cc reaches v cc(on) , typically 9.5 v, the startup current source is disabled. the current source is enabled once v cc falls below v cc(off1) , typically 9.4 v, while faults are present. once faults are removed and the controller is operating, the startup current source turn?on threshold is reduced to v cc(off2) , typically 7.5 v.. 14 outm main switch gate control. outm can source 2 a and sink 3 a. 15 pgnd ground connection for outm and outa. tie to the power stage return with a short loop. 16 outa active clamp switch gate control. outa has an adjustable leading and trailing edge overlap delay against outm. outa can source 2 a and sink 1 a. 17 flt/sd fault report and shutdown control. this is a dual?function bi?directional pin. this pin is an open?collector output with a 10 k internal pull?up resistance connected to ref. 18 refa internally connected to ref. 19 uvlo input voltage undervoltage detector. the input voltage is scaled down and sampled by means of a resistor divider. the controller enters standby mode once the uvlo voltage, v uvlo , exceeds the standby threshold, v stby , typically 0.4 v. the controller enters shutdown mode if v uvlo falls below v stby by the shutdown hysteresis level. the controller is enabled once v uvlo exceeds the enable threshold, v enable , typically 1.25 v. hysteresis is provided by an internal pull?down current source, i uvlo , typically 20 a. the current source is disabled once the controller is enabled. 20 nc no connect (creepage distance). 21 nc no connect (creepage distance).
ncp1565 www. onsemi.com 6 detailed pin description pin number function name 22 v in high voltage startup circuit input. connect the input line voltage directly to this pin to enable the internal startup regulator. a constant current source supplies current from this pin to the capacitor connected to the vcc pin, eliminating the need for a startup resistor. the minimum charge current is 40 ma. the operating voltage range of the startup circuit is 13 v to 120 v. 23 nc no connect (creepage distance). 24 vsclamp volt?second clamp. an external r?c divider from the input line generates a voltage ramp. this ramp is compared to a voltage reference, v slimit , typically 1.5 v. the outm pulse is terminated once the ramp voltage exceeds v slimit , thus limiting the maximum volt?second product of the main transformer. in voltage mode, vsclamp and ramp pins can be tied together to share one external r?c circuit. maximum ratings (notes 1 through 3) rating symbol value unit high voltage startup circuit input voltage v in ?0.3 to 120 v high voltage startup circuit input current i in 70 ma uvlo input voltage v uvlo ?0.3 to v cc v otp input voltage v otp ?0.3 to 7 v ramp input voltage v ramp ?0.3 to 7 v ramp peak input current i ramp 1 a vsclamp input voltage v sclamp ?0.3 to 7 v vsclamp input current i sclamp 0.5 ma rt input voltage v rt ?0.3 to 7 v rt input current i rt 2 ma comp input voltage v comp ?0.3 to 5.5 v comp input current i comp 1 ma reference input voltage v ref ?0.3 to 5.5 v reference input current i ref 20 ma supply input voltage v cc(max) ?0.3 to 20 v supply input current i cc(max) 70 ma main driver maximum voltage v outm ?0.3 to v cc v main driver maximum current i outm(src) i outm(snk) 2 3 a active clamp driver maximum voltage v outa ?0.3 to v cc v active clamp driver maximum current i outa(src) i outa(snk) 2 1 a current sense input voltage v cs ?0.3 to 5.5 v current sense peak input current i cs 0.5 a soft?start input voltage v ss ?0.3 to 5.5 v restart input voltage v res ?0.3 to 5.5 v restart peak input current i res 0.1 a flt/sd input voltage v flt/sd ?0.3 to 7 v flt/sd peak input current i flt/sd 0.1 a deadtime input voltage v dt ?0.3 to 5.5 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 2. as specified for a jedec eia/jesd 51.3 conductivity test. test conditions were under natural convection of zero air flow. 3. v in is the exception.
ncp1565 www. onsemi.com 7 maximum ratings (notes 1 through 3) rating unit value symbol maximum duty ratio control input voltage v dlmt ?0.3 to 5.5 v maximum duty ratio control input current i dlmt 2 ma maximum operating junction temperature t j ?40 to 150 c storage temperature range t stg ?60 to 150 c lead temperature (soldering, 10 s) t l(max) 300 c moisture sensitivity level msl 1 ? power dissipation (t a = 25 c, 1 oz cu (35 m), 0.155 sq inch (100 mm 2 ) printed circuit copper clad) mntxg suffix, plastic package (qfn?24) p d 760 mw thermal resistance, junction?to?ambient 1 oz cu (35 m) 2?layer 100 mm 2 printed circuit copper clad (note 3) mntxg suffix, plastic package (qfn?24) r ja 131 c/w thermal resistance, junction?to?ambient 2 oz cu (70 m) 2?layer 100 mm 2 printed circuit copper clad (note 3) mntxg suffix, plastic package (qfn?24) r ja 115 c/w esd capability human body model per jedec standard jesd22?a114f. machine model per jedec standard jesd22?a115c. charge device model per jedec standard jesd22?c101e. > 2000 > 200 > 1500 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 2. as specified for a jedec eia/jesd 51.3 conductivity test. test conditions were under natural convection of zero air flow. 3. v in is the exception. electrical characteristics : (c ref = 0.1 f, v in = 48 v, v uvlo = 2 v, v cc = 10 v, v cs = 0.25 v, r dlmt = 49.9 k , r dt = 100 k , r t = 100 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics conditions symbol min typ max unit startup and supply circuits supply voltage upper regulation level lower regulation while disabled lower regulation while enabled minimum operating voltage reset voltage v cc increasing v cc decreasing v cc decreasing v cc decreasing v cc decreasing v cc(on) v cc(off1) v cc(off2) v cc(min) v cc(reset) 9.1 9.0 7.3 6.2 6.1 9.5 9.4 7.5 6.5 6.4 9.9 9.8 7.7 6.8 6.7 v startup delay delay from v cc(on) to enable t delay(start) 30 ? 125 s delay in turning start?up source off v cc > v cc(off2) t vcc(off2) 3 10 s delay in turning start?up source on v cc < v cc(off2) t vcc(on2) 15 30 s startup current v cc = v cc(on) ? 0.2 v, v in = 48 v i start 40 55 ? ma startup circuit off?state leakage current v in = 120 v i vin(off) ? ? 100 a minimum startup voltage i start = 15 ma, v cc = v cc(on) ? 0.2 v v in(min) ? ? 15 v supply current disabled mode current standby no switching operating current uvlo below 0.4 v v cc = 10 v, v uvlo = 1 v v cc = 10 v, i comp = 850 a f = 200 khz, c outm = c outa = open i cc1 i cc2 i cc3 i cc4 ? ? ? ? ? ? ? 2 2 4 5 ma reference reference voltage i ref = 0 ma v ref 4.9 5.0 5.1 v load regulation i ref = 0 to 10 ma v ref(load?reg) 4.85 5.00 5.15 v step load response i ref = 5 to 10 ma, di/dt = 100 ma/ s v ref(step?reg) 4.85 5.00 5.15 v source current v ref = 4.75 v i ref(max) 12 ? ? ma product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. guaranteed by design. not tested. 5. guaranteed by design.
ncp1565 www. onsemi.com 8 electrical characteristics : (c ref = 0.1 f, v in = 48 v, v uvlo = 2 v, v cc = 10 v, v cs = 0.25 v, r dlmt = 49.9 k , r dt = 100 k , r t = 100 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions reference minimum capacitance (note 4) c ref(range) 0.1 ? ? f reference undervoltage threshold v ref increasing v ref(uvlo) 4.5 4.75 v reference undervoltage hysteresis v ref decreasing v ref(hys) 200 mv line voltage uvlo standby threshold v uvlo increasing v stby 0.35 0.40 0.45 v standby hysteresis v uvlo decreasing v stby(hys) 0.05 0.10 0.15 v enable threshold v uvlo increasing v enable 1.23 1.25 1.27 v disable filter delay v uvlo = v enable ? 400 mv t enable(delay2) 0.5 ? 1 s pull?down current in standby mode v uvlo = v enable - 0.1 v v shdn < v uvlo < v enable i stby 18 20 22 a pull?down current enable threshold i stby(thd) ? v cc(off2) ? v pull?down resistor while i stby is disabled v uvlo = 1.25 v r uvlo 22.4 32.0 41.6 k main gate drive rise time (10?90%) from 10% to 90% of v outm , c outm = 2.2 nf t outm(rise) ? 8.8 17.6 ns fall time (90?10%) 90% to 10% of v outm , c outm = 2.2 nf t outm(fall) ? 6.0 12 ns current capability source sink v outm = 4 v v outm = 4 v, v cc = 7.5 v, i comp = 850 a i outm(src) i outm(snk) 2 3 ? ? a high state voltage offset v cc ? v outm , v cc = 8 v, c outm = 2.2 nf v outm(offset) ? ? 0.2 v low stage voltage v uvlo = 1 v v outm(low) ? ? 0.2 v active clamp gate drive rise time (10?90%) from 10 to 90% of v outa , c outa = 2.2 nf t outm(rise) ? 8.8 17.6 ns fall time (90?10%) 90 to 10% of v outa , c outa = 2.2 nf t outm(fall) ? 17.6 35.2 ns current capability source sink v outa = 4 v v outa = 4 v, v cc = 7.5 v i outa(src) i outa(snk) 2 1 ? ? a high state voltage offset v cc ? v outa , v cc = 8 v, c outa = 2.2 nf v outa(offset) ? ? 0.2 v low stage voltage v uvlo = 1 v v outa(low) ? ? 0.2 v current sense average current limit threshold v ilim(ave) 288 300 312 mv average current limit leading edge blanking duration (note 4) t ilimave(leb) 23 30 37 ns average current limit propagation delay (note 4) t ilimave(delay) ? 40 ? ns cycle by cycle current limit threshold v ilim 432 450 468 mv cycle by cycle current limit leading edge blanking duration t ilim(leb) 42 55 68 ns cycle by cycle current limit propagation delay step v cs to 0.7 v to outm falling edge, dv/dt = 20 v/ s t ilim(delay) ? 40 56 ns short circuit current limit threshold v ilim(sc) 672 700 728 mv short circuit current limit leading edge blanking duration t ilimsc(leb) 23 30 37 ns short?circuit current limit propagation delay step v cs to 0.9 v to outm falling edge, dv/dt = 10 v/ s t ilimsc(delay) ? 40 56 ns short circuit counter step v cs to v ilim(sc) + 0.2 v n ilimsc ? 2 ? ? discharge switch on resistance v sclamp = 2 v, v cs = 100 mv r csswitch(on) ? ? 35 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. guaranteed by design. not tested. 5. guaranteed by design.
ncp1565 www. onsemi.com 9 electrical characteristics : (c ref = 0.1 f, v in = 48 v, v uvlo = 2 v, v cc = 10 v, v cs = 0.25 v, r dlmt = 49.9 k , r dt = 100 k , r t = 100 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions overtemperature protection (otp) overtemperature detect threshold v otp increasing v otp(th) 1.23 1.25 1.27 v overtemperature detect delay v otp = v otp(th) ? 20 mv t otp(delay) 10 20 30 s pull?up current in otp mode v otp = v otp(th) + 0.1 v i otp 18 20 22 a soft?start soft?start charge current v ss = 1.5 v to 3 v i ss 18 20 22 a soft?start onset threshold v ss(offset) 1.35 v clamp voltage v ss(clamp) 0.85 v discharge switch on resistance v ss = 100 mv r ssswitch(on) ? ? 30 disable threshold v ss decreasing v ss(disable) 0.4 0.5 0.6 v restart restart delay threshold v res increasing v res(th) 0.96 1.00 1.04 v peak voltage v cs > v ilimave , v res increasing v res(peak) 3.8 4.0 4.2 v valley voltage v cs > v ilimave , v res decreasing v res(valley) 1.9 2.0 2.1 v discharge current v cs < v ilimave , v res = 100 mv i res(snk) 4 5 6 a charge current v cs > v ilimave , v res = v res(valley) ? 50 mv v cs > v ilimave , v res = v res(valley) + 50 mv i res(src1) i res(src2) 18 4 20 5 22 6 a restart counter v otp > v otp(th) n res 32 discharge voltage v res(dis) 50 100 150 mv discharge switch on resistance v res = 200 mv r esswitch(on) ? ? 110 fault report and remote shutdown enable threshold v flt/sd = increasing v flt(enable) 1.37 1.45 1.53 v fault threshold v flt/sd = decreasing v faultflt/sd 1.23 1.25 1.27 v internal pull?up resistor v flt/sd = 3 v r fault/sd 8.5 10.0 11.5 k discharge switch on resistance v flt/sd = 100 v r faultswitch(on) ? ? 120 oscillator operating frequency range (note 5) f range 100 ? 1500 khz oscillator frequency t d1 100 ns t d1 75 ns r t = 49.9 k , r dt = 69.8 k , r dlmt = 26.7 k r t = 16.2 k , r dt = 52.3 k , r dlmt = 9.09 k f osc1 f osc2 180 540 200 600 220 660 khz maximum duty ratio maximum duty ratio f sw = 200 khz f sw = 600 khz internal spec is 3%, v uvlo = 1.4 v r t = 49.9 k , r dt = 69.8 k , r dlmt = 41.2 k r t = 49.9 k , r dt = 69.8 k , r dlmt = 34.0 k r t = 49.9 k , r dt = 69.8 k , r dlmt = 26.7 k r t = 16.2 k , r dt = 52.3 k , r dlmt = 14.0 k r t = 16.2 k , r dt = 52.3 k , r dlmt = 11.5 k r t = 16.2 k , r dt = 52.3 k , r dlmt = 9.09 k d (max1a) d (max2a) d (max3a) d (max1b) d (max2b) d (max3b) 76.5 62.8 48.8 76.2 62.1 47.8 80.5 66.1 50.3 80.2 65.4 49.3 84.5 69.4 53.8 84.2 68.7 52.8 % minimum duty ratio i comp = 850 a d (min) ? ? 0 % volt?second clamp volt second limit voltage threshold i comp = 0 a v slimit 1.44 1.50 1.56 v volt?second propagation delay step v sclamp to 2 v to outm falling edge, dv/dt = 10 v/ s t vsclamp 40 60 ns vsclamp switch on resistance v sclamp = 100 mv r vsclampswitch(on) ? ? 45 vsclamp input leakage current v sclamp = 1.4 v i vsclamp(leak) ? ? 100 na overlap time delay overlap delay range (note 5) include uvlo adjustment. but not cs. t d(range) 20 ? 500 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. guaranteed by design. not tested. 5. guaranteed by design.
ncp1565 www. onsemi.com 10 electrical characteristics : (c ref = 0.1 f, v in = 48 v, v uvlo = 2 v, v cc = 10 v, v cs = 0.25 v, r dlmt = 49.9 k , r dt = 100 k , r t = 100 k , for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions overlap time delay overlap delay from outa to outm rising edges r dt = 52.3 k , v uvlo = 2.5 v, v cs = 0.4 v r dt = 52.3 k , v uvlo = 2.5 v, v cs = 0.05 v r dt = 69.8 k , v uvlo = 2.5 v, v cs = 0.4 v r dt = 69.8 k , v uvlo = 1.5 v, v cs = 0.05 v r dt = 274 k , v uvlo = 3 v, v cs = 0.4 v r dt = 274 k , v uvlo = 3 v, v cs = 0.05 v t d1a t d1b t d1c t d1d t d1e t d1f 47.3 56.8 63.1 107.1 206.5 259.9 63 95 84 179 275 433 78.8 132.6 105.2 250 344.2 606.4 ns overlap delay from outm to outa falling edges r dt = 52.3 k , v uvlo = 2.5 v, v cs = 0.4 v r dt = 52.3 k , v uvlo = 2.5 v, v cs = 0.05 v r dt = 69.8 k , v uvlo = 2.5 v, v cs = 0.4 v r dt = 69.8 k , v uvlo = 1.5 v, v cs = 0.05 v r dt = 274 k , v uvlo = 3 v, v cs = 0.4 v r dt = 274 k , v uvlo = 3 v, v cs = 0.05 v t d2a t d2b t d2c t d2d t d2e t d2f 31.2 37.5 41.6 70.7 136.3 171.5 42 63 56 118 182 286 52 87.5 69.4 165 227.2 400.2 ns ratio from t d1 to t d2 ? 0.66 ? ramp pwm propagation delay step v ramp to 2 v to outm falling edge, dv/dt = 10 v/ s t pwm 40 60 ns pwm offset voltage v pwm(offset) 1.35 v discharge switch on resistance v ramp = 100 mv r ampswitch(on) ? ? 25 ramp input leakage current v ramp = 1.8 v i ramp(leak) ? ? 100 na thermal shutdown thermal shutdown temperature increasing t shdn 150 165 ? c thermal shutdown hysteresis temperature decreasing t shdn(hys) ? 20 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. guaranteed by design. not tested. 5. guaranteed by design.
ncp1565 www. onsemi.com 11 typical operating characteristics t j , junction temperature ( c) figure 4. turn?on voltage variation vs. junction temperature v cc(on) (v) 9.9 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 5. turn?off voltage 1 variation vs. junction temperature v cc(off1) (v) 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 6. turn?off voltage 2 variation vs. junction temperature v cc(off2) (v) 7.7 ?50 ?30 ?10 10 30 50 70 90 110 130 7.65 7.6 7.55 7.5 7.45 7.4 7.35 7.3 t j , junction temperature ( c) figure 7. minimum operating voltage variation vs. junction temperature v cc(min) (v) 6.8 ?50 ?30 ?10 10 30 50 70 90 110 130 6.7 6.6 6.5 6.4 6.3 6.2 t j , junction temperature ( c) figure 8. reset voltage variation vs. junction temperature v cc(reset) (v) 6.7 ?50 ?30 ?10 10 30 50 70 90 110 130 6.6 6.5 6.4 6.3 6.2 6.1 t j , junction temperature ( c) figure 9. start?up current variation vs. junction temperature i start (v) ?40 ?50 ?30 ?10 10 30 50 70 90 110 130 ?45 ?50 ?55 ?60 ?65 ?70 ?75 ?80
ncp1565 www. onsemi.com 12 typical operating characteristics t j , junction temperature ( c) figure 10. minimum startup voltage on the hv pin variation vs. junction temperature v in(min) (v) 15.0 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 11. operating current in disabled mode vs. junction temperature i cc1(uvlo=0v) (ma) 1.9 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 12. operating current in standby mode vs. junction temperature i cc2(vuvlo=1v) (ma) 1.9 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 13. operating current in active mode but without switching vs. junction temperature i cc3(icomp=850 a) (ma) 3.9 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 14. operating current while switching without load on driver outputs vs. junction temperature i cc4(200khz no load) (ma) 5.0 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 15. fault pin activation level vs. junction temperature v fault (flt/sd) 1.270 ?50 ?30 ?10 10 30 50 70 90 110 130 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.7 1.5 1.3 1.1 0.9 0.7 3.7 3.5 3.3 3.1 2.9 2.7 2.5 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230
ncp1565 www. onsemi.com 13 typical operating characteristics t j , junction temperature ( c) figure 16. reference voltage variation vs. junction temperature v ref (v) 5.10 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 17. standby threshold variation vs. junction temperature v stby (v) 0.45 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 18. enable voltage variation vs. junction temperature v enable (v) 1.270 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 19. average current limit threshold variation vs. junction temperature v ilimave (mv) ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 20. cycle by cycle current limit threshold variation vs. junction temperature v ilim (mv) 467 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 21. short?circuit current limit threshold variation vs. junction temperature v ilimsc (mv) 617 ?50 ?30 ?10 10 30 50 70 90 110 130 308 5.08 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 4.90 0.44 0.43 0.42 0.41 0.40 0.39 0.38 0.37 0.36 0.35 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 303 298 293 288 462 457 452 447 442 437 432 612 607 602 597 592 587 582
ncp1565 www. onsemi.com 14 typical operating characteristics t j , junction temperature ( c) figure 22. otp threshold variation vs. junction temperature v otp(th) (v) 1.270 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 23. otp current variation vs. junction temperature i otp ( a) 22.0 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 24. oscillator frequency variation vs. junction temperature (f sw = 200 khz) fosc1 (khz) 220 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 25. oscillator frequency variation vs. junction temperature (f sw = 600 khz) fosc2 (khz) ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 26. oscillator frequency variation vs. junction temperature (f sw = 1.5 mhz) fosc3 (khz) 1700 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 27. maximum duty ratio variation vs. junction temperature (f sw = 200 khz) dmax1a(200khz) (%) 84.5 ?50 ?30 ?10 10 30 50 70 90 110 130 660 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 215 210 205 200 195 190 185 180 640 620 600 580 560 540 1650 1600 1550 1500 1450 1400 1350 83.5 82.5 81.5 80.5 79.5 78.5 77.5 76.5
ncp1565 www. onsemi.com 15 typical operating characteristics t j , junction temperature ( c) figure 28. maximum duty ratio variation vs. junction temperature (f sw = 200 khz) dmax2a(200khz) (%) 68.8 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 29. maximum duty ratio variation vs. junction temperature (f sw = 200 khz) dmax3a(200khz) (%) 53.8 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 30. maximum duty ratio variation vs. junction temperature (f sw = 600 khz) dmax1b(600khz) (%) 84.2 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 31. maximum duty ratio variation vs. junction temperature (f sw = 600 khz) dmax2b(600khz) (%) ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 32. maximum duty ratio variation vs. junction temperature (f sw = 600 khz) dmax3b(600khz) (%) 52.8 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 33. volt?second limit vs. junction temperature v slimit (v) 1.56 ?50 ?30 ?10 10 30 50 70 90 110 130 68.1 67.8 66.8 65.8 64.8 63.8 62.8 53.3 52.8 52.3 51.8 51.3 50.8 50.3 49.8 49.3 48.8 83.2 82.2 81.2 80.2 79.2 78.2 77.2 76.2 67.1 66.1 65.1 64.1 63.1 62.1 52.3 51.8 51.3 50.8 50.3 49.8 49.3 48.8 48.3 47.8 1.54 1.52 1.50 1.48 1.46 1.44
ncp1565 www. onsemi.com 16 typical operating characteristics t j , junction temperature ( c) figure 34. shutdown pulse volt?second limit vs. junction temperature v slimit(shdn) (v) 1.87 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 35. volt?second switch?on resistance variation vs. junction temperature r vsclampswitch(on) ( ) 45 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 36. overlap delay outa to outm variation vs. junction temperature t d1c(141.5) (ns) 176.125 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 37. overlap delay outm to outa variation vs. junction temperature t d2a(56) (ns) ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 38. overlap delay outa to outm variation vs. junction temperature t d1a(85) (ns) 103.75 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 39. overlap delay outa to outm variation vs. junction temperature t d1b(121) (ns) ?50 ?30 ?10 10 30 50 70 90 110 130 67 1.85 1.83 1.81 1.79 1.77 1.75 1.73 40 35 30 25 20 15 10 5 0 166.125 156.125 146.125 136.125 126.125 116.125 106.125 62 57 52 47 42 150.75 140.75 130.75 120.75 110.75 90.75 100.75 98.75 93.75 88.75 83.75 78.75 73.75 68.75 63.75
ncp1565 www. onsemi.com 17 typical operating characteristics t j , junction temperature ( c) figure 40. overlap delay outm to outa variation vs. junction temperature t d2b(80.2) (ns) 100.15 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 41. overlap delay outm to outa variation vs. junction temperature t d2c(93.4) (ns) 115.05 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 42. pulse width modulator delay variation vs. junction temperature p wmpropdelay (ns) 60 ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 43. pulse width modulator offset variation vs. junction temperature p pwmoffset (ns) ?50 ?30 ?10 10 30 50 70 90 110 130 t j , junction temperature ( c) figure 44. current sense pin discharge switch r ds(on) variation vs. junction temperature r csswitch(on) (ns) 32 ?50 ?30 ?10 10 30 50 70 90 110 130 1.5 95.15 90.15 85.15 80.15 75.15 70.15 65.15 60.15 110.05 105.05 95.05 90.05 85.05 80.05 75.05 70.05 50 40 30 20 10 0 1.4 1.3 1.2 1.1 1.0 27 22 17 12 7 2
ncp1565 www. onsemi.com 18 application information the ncp1565 is a highly?integrated dual?mode active clamp pwm controller targeting next?generation high?density, high?performance and small to medium power level isolated dc?dc converters for use in telecom and datacom applications. operating up to 1.5 mhz, the part can be configured in either voltage mode control with input voltage feedforward or peak?current mode control. an adjustable adaptive overlap time between the main power and the active clamp mosfets optimizes system ef ficiency based on input voltage and load conditions enabling higher efficiency and greater power density solutions. this controller integrates all the necessary control and protection functions to implement an isolated active?clamp forward or asymmetric half?bridge converter with synchronous rectification. it integrates a high?voltage startup bias regulator directly connected to the dc input, up to 120 v. the ncp1565 protection features include: ? a line undervoltage detector to stop operation in case the input rail collapses below a programmable level ? a two?threshold cycle?by?cycle current limit which allows to detect short circuit situations but also overload conditions on the dc?dc converter output ? a line voltage?dependent maximum duty ratio limit to safely operate the forward transformer ? a programmable over temperature protection using an external ntc sensor ? an adjustable re?start time to force an auto?recovery hiccup mode in presence of the above faults the part includes a dedicated pin fl t/sd for signaling the presence of a fault condition. the pin can be used as an input to shutdown the controller using an external signal. the controller also features an adjustable restart time. high?voltage start up circuit the ncp1565 integrates a high voltage startup circuit accessible by the v in pin. the startup circuit is rated up to a maximum voltage of 120 v. the startup regulator consists of a constant current source that supplies current from a high?voltage rail to the supply capacitor on the v cc pin (cv cc ). the startup circuit current (i start ) is 40 ma minimum. the internal high voltage startup circuit eliminates the need for external startup components. in addition, this regulator reduces no?load power and increases the system efficiency as it uses negligible power in the normal operation mode. the startup circuit is configured to operate in the so?called dynamic self?supply (dss) mode in certain conditions. in this dss mode, v cc hiccups between two levels (9.5 v and 9.4 v typically) and self supplies the ic in lack of auxiliary supply. this mode can be briefly entered at startup (fault clearance delay) but it is mainly activated in a fault state or in lack of auxiliary v cc : in this mode, as no external supply is present, the dss block permanently maintains the controller supply until the auxiliary v cc comes back. this is the case for instance in deep dcm mode when the part skips cycle. v cc can no longer be maintained (pulses are too narrow) and v cc collapses until it hits 7.5 v. at this point, the dss takes over. please make sure power dissipation in this mode respects the maximum power dissipation capability of the controller. a typical startup sequence commences with the charge of the v cc capacitor up to the startup threshold v cc(on) , 9.5 v typically. once this threshold is reached, the current source turns off and the part starts its own internal initialization: it resets all registers, charges the soft?start capacitor above 0.5 v, makes sure all the fault inputs are cleared (flt/sd is high, the overtemperature protection (otp) input is low and the input voltage sensed by the uvlo input is within acceptable limits). as the v cc capacitor is alone to supply the controller during this startup time, the level across its terminals falls and eventually reaches v cc(off1) , typically 9.4 v, especially if some faults are still present at startup. at this point, the current source turns back on until v cc reaches v cc(on) , again: a hiccup takes place and lasts until the part is ready to switch, i.e. all faults are cleared. once internal flags are ready, an extra delay is added, t delay(start) , before the part is actually enabled and switches. after the enable signal has been asserted, the v cc uvlo level drops to v cc(off2) , typically 7.5 v during the initialization sequence, the main power mosfet is not switching, outm is low. on the opposite, to allow the immediate availability of the low?side p?channel active clamp switch, its dedicated output outa is raised to v cc when the 9.5 v threshold is reached. this is to allow the pre?charge of the p?channel charge pump capacitor and makes it ready for operation. while the part is enabled, the voltage on the soft?start (ss) capacitor is slowly rising up and when it crosses the internal 1.35 v of fset, outm starts to produce low duty ratio pulses, driving the forward converter main power mosfet. please note that while the internal enable flag is not asserted (during the initialization sequence or during a fault), the voltage on the ss pin is clamped to 0.85 v, naturally putting the part in ready?to?pulse mode whenever enable gets asserted. at the end of the initialization sequence, the controller stops the high?voltage startup source and v cc drops as the auxiliary voltage did not build up yet. before reaching the lower regulation threshold, v cc(off2) , typically 7.5 v, the auxiliary winding must have appeared to take over the controller supply. you will size the v cc capacitor in that way. if for any reason the auxiliary winding did not build up before v cc reaches 7.5 v, the current source turns back on again to maintain the controller supply in a kind of non?regulated hysteretic mode... in this dss mode, the current capability is 40 ma at minimum and you have to make sure the internal ic consumption (including driving current) is well below 40 ma. during this mode, the average current absorbed by the v in pin is roughly the average
ncp1565 www. onsemi.com 19 current consumed by the part. care must be taken to ensure that a low current is absorbed while in the upper input voltage range. failure to respect this fact will damage the controller by overheat. in case an accidental overload of the dss would occur (you consume too much on the v cc pin and the dss cannot maintain v cc ), the voltage would drop to v cc(min) , typically 6.5 v. in this mode, the part restarts after a start?up sequence. a typical successful start?up sequence appears in figure 45 while it fails in figure 46 as the current absorbed from the v cc is too high. in this case, the part restarts again for another attempt. figure 45. a typical startup sequence in which the auxiliary voltage builds up in time 9.5 v 9.4 v 7.5 v 6.5 v 4 v 1.35 v 0.5 v pwm pulses all cleared enabled v cc v ss figure 46. in this figure, the auxiliary voltage did not build up in time, aborting the startup sequence v ss internal reset fault cleared aux winding does not build?up pwm stops ss reset uvlo pwm stops ss reset pwm pulses pwm pulses 9.5 v 9.4 v 7.5 v 6.5 v 4 v 1.35 v 0.5 v 1 v v cc t t too much current for dss
ncp1565 www. onsemi.com 20 figure 47. in this figure, the vcc capacitor is small and is getting help from the dss until the auxiliary voltage eventually takes off v ss internal reset fault cleared aux winding does not build?up uvlo pwm pulses 9.5 v 9.4 v 7.5 v 6.5 v 4 v 1.35 v 0.5 v 1 v v cc t t aux winding builds up dss takes over for a moment. the v cc capacitor must be sized such that a v cc voltage greater than v cc(off2) is maintained while the auxiliary supply voltage is building up. however, if the capacitance has adversely dropped because of extreme temperatures conditions for instance, it can happen that v cc drops too fast and the dss is activated. this is what figure 47 shows. dss takes over until v cc aux builds up. again, care must be taken to ensure that part power dissipation remains within acceptable limits. the operating ic bias current, i cc4 , and gate charge load at the drive outputs must be considered to correctly size cv cc . to size this capacitor, you must account for the mosfet drive current. the average current absorbed from the v cc capacitor at startup depends on the switching frequency f sw and the total gate charge q g as follows: i drv f sw q g (eq. 1) assume we picked a 40 nc gate?charge mosfet operated at 200 khz. the average current absorbed by the driver will be: i drv 200k 40n 8ma (eq. 2) the capacitor value depends on several parameters: ? the allowed voltage drop before the controller activates the dss at 7.5 v. this drop is 2 v, from 9.5 v to 7.5 v. ? the current sourced by the capacitor while the auxiliary winding is building up. it is made of equation 1 plus the internal controller consumption, i cc4 (4 ma at 200 khz). ? the time taken by the auxiliary winding to build up is more difficult to assess given the numerous parameters at play: primary?side current limit, soft?start duration, output capacitance and so on. simulations in worst?case give us an estimated time of 5 ms for the auxiliary supply to reach 8 v. with these parameters on hand, the v cc capacitor can be evaluated: cv cc i drv i ccr t startup v 12m 5m 2 30 f (eq. 3) a 47 f capacitor is a possible choice. figure 47 illustrates a typical start?up sequence.
ncp1565 www. onsemi.com 21 figure 48. this sketch shows how the vcc capacitor can be sized to avoid tripping the dss circuit at start?up t v cc 9.5 v 9.4 v 7.5 v 6.5 v startup t pwm pulses 1.3v ss v = v ? 2 v if power dissipation is under control during start up, you can reduce the capacitor value given by equation 3 and implement the start?up scheme shown in figure 46. demonstration boards with 1?2 f v cc capacitors have shown proper operation with these values. line undervoltage detector the ncp1565 monitors the line voltage and enables the controller when the input voltage is within the required range. the input voltage is also used for modulating the drivers overlap time as we will see later. the input voltage is sampled using a resistor divider and applied to the uvlo pin. a small bypass capacitor is recommended for noise filtering. the uvlo input can be used as an enable/disable function. figure 49 shows the uvlo detector architecture. by monitoring the voltage on the uvlo pin, the controller can be put in three different modes: disable, standby and enable. the controller enters standby mode once the uvlo voltage, v uvlo , exceeds the standby threshold, v stby , typically 0.4 v. the standby mode features a 100 mv hysteresis, v stby(hys) , which, added to a 1.5 s delay, provides adequate noise immunity. in standby mode, v cc hiccups between 9.5 and 9.4 v, the reference voltage is maintained. the flt/sd pin is pulled low to signal the uvlo. figure 49 illustrates an input voltage drop that keeps v uvlo above 0.4 v, putting the part into standby mode. the controller transitions into the enable mode once v uvlo exceeds v enable , typically 1.25 v. once in enable mode, the controller is allowed to start if no other faults are present. an internal pull?down current source, i stby , provides hysteresis. it is typically 20 a. i stby turns off once the controller is enabled, allowing v uvlo to rise above v enable by the hysteresis level set by r 1 . the controller is disabled if v uvlo falls below v enable , at which point i stby is re?enabled creating a voltage drop on the uvlo pin. a maximum delay of 1 s, t enable(delay) , on the enable comparator provides noise immunity. i stby is disabled while v cc is below v cc(off2) during power up or if v cc falls below v cc(reset) after i stby has been enabled. figure 49. uvlo block diagram the resistor divider is selected such that v uvlo exceeds v enable at the desired input voltage. equation 4 is used to calculate the startup voltage level, v in(start) . equation 5 is used to calculate the minimum operating voltage, v in(min) . v in(start) v enable r 1 r 2 r 2 r 1 i stby (eq. 4) v in(min) v enable r 1 r 2 r 2 (eq. 5) a pull?down transistor and resistor combination, sw uvlo and r uvlo , ensure v uvlo is below v enable while i stby is disabled. this prevents the controller from incorrectly turning on while v uvlo settles.
ncp1565 www. onsemi.com 22 figure 50. the part starts up while v in is ok. v in now decreases to 0, shutting off the part. v in is back again shortly after, restarting the part. soft?start soft?start slowly increases the duty ratio during power up, allowing the controller to gradually reach steady?state operation by slowly increasing the output voltage while reducing startup circuit stress. the duty ratio is controlled by comparing the ss pin voltage, v ss , to the vsclamp pin voltage, v sclamp . v sclamp is level?shifted by 1.35 v before comparing it to v ss . this ensures a minimum duty ratio of 0%. v ss is slowly increased by charging the soft?start capacitor with a fixed current source, i ss , typically 20 a. outm is disabled once the peak voltage of v sclamp exceeds v ss . the soft?start pin is internally grounded while a fault is present. current sense a signal proportional to the current across the main switch is applied to the cs pin. the current sense information is used to calculate the average primary current to modulate the drivers overlap time and implement overcurrent protection (ocp). it is also used for cycle by cycle peak current limit control and detecting a short circuit condition. figure 50 shows the block diagram of the current limit circuitry. figure 51. the current limit circuitry implements three distinct comparators cs>csth2 cs res c res vref 20ua 5ua + _ + _ csth1 =0.5v csth2 =0.75v ocp scp leb ioavg emulation csavg>csth1 csavgcsth3 + _ csth3 =1.0v cycle?by?cycle current limit terminate pwm pulse & discharge pwm ramp shutdown & restart triggered for 2 (two) consecutive cycles csavg = 0.45 v = 0.7 v = 0.3 v
ncp1565 www. onsemi.com 23 the controller can identify three different types of overcurrent conditions: ? regular current pulse: in a forward converter normal operation, the primary current is made of the reflected inductor current to which adds the primary magnetizing current. when the voltage image of this current exceeds the feedback setpoint (in current mode) or the maximum sense voltage (0.45 v typical in voltage mode), the current pulse is terminated. ? short?circuit pulse: if an abnormally?high current pulse is detected (0.7 v) for two consecutive clock pulses, the part shuts off and goes into restart mode. this can happen during a winding short circuit or in presence of a defective component in the secondary side. ? overcurrent condition: in case the converter?s output is overloaded, the average input current will increase, reflecting the average input power increase. the ncp1565 averages the primary?side current sense information and when it exceeds a certain value, a shutdown delay starts. when this delay elapses, the part shuts off and goes into restart mode. an internal leading edge blanking (leb) circuitry masks the current sense information before applying it to the current monitoring circuitry. leb prevents unwanted noise from terminating the drive pulses prematurely. it is recommended to place a small rc filter close to the cs pin to suppress noise. the leb period begins once v outm reaches approximately 2 v. to improve the pin noise immunity, an internal switch, r cs(switch) , discharges and holds the cs pin low at the conclusion of every cycle. the switch is enabled while the main driver is low. the maximum impedance of the switch, is 20 . the average information is reconstructed from the cs information and used to determine the ocp shutdown delay. once the average current information, c s(avg) , exceeds v ilim(ave) , typically 0.3 v, the 5 a pull?down current source, i res(snk) , is disabled and the 20 a pull?up current source, i res(src1) , is enabled to charge the res capacitor. the average current information is blanked by the t ilimave(leb) timer, typically 30 ns. as long as an overcurrent is sensed, the capacitor connected to the res pin continues its charge. if the overcurrent disappears, the 20 a source stops and the capacitor discharges with the 5 a pull?down source. if the overcurrent comes back again, the 20 a source takes over and lifts the capacitor voltage towards the 1 v threshold. when it is reached, the part stops all operations and goes into restart mode: 32 up/down voltage cycles between 2/4 v are counted on the res pin before an attempt to restart occurs. cycle by cycle peak current limit protection is implemented using the cycle?by?cycle comparator. it terminates the drive pulse if the cs voltage exceeds v ilim , typically 0.45 v. the cycle?by?cycle current information is blanked by the t ilim(leb) timer, typically 55 ns. the cycle?by?cycle comparator propagation delay, t ilim(delay) , is typically 40 ns. cycle?by?cycle peak current limit protection is available in all operating modes. the short circuit comparator protects the controller during a winding short circuit condition for instance. the comparator terminates the drive pulse if the cs voltage exceeds v ilim(sc) , typically 0.7 v. the short circuit current information is blanked by the t ilimsc(leb) timer, typically 30 ns. the short circuit comparator propagation delay, t ilimsc(delay) , is typically 40 ns. two consecutive short circuit conditions cause the controller to enter restart mode without a shutdown delay. figure 52 shows simulation waveforms during a short circuit fa ult. once the overcurrent fault is detected the main driver operates at minimum on time. at the third internal clock cycle, the short circuit condition is confirmed and a restart sequence is initiated. in restart mode, v cc is hiccupping between v cc(on) and v cc(off1) and the soft?start capacitor is discharged. figure 52. a short circuit occurs and shuts down the part after two consecutive pulses the current sense signal is generated using either a current sense resistor or current sense transformer. in both instances, good pcb layout practices are required to ensure correct operation of the current sense detection circuitry. a few are listed below:
ncp1565 www. onsemi.com 24 1. the current sense filter capacitor must be placed as close as possible to the ic and referenced to the agnd pin. 2. when using a current sense transformer both leads of the transformer secondary should be routed to the filter network located very close to the ic. 3. low current signals should all be connected to the agnd net. agnd should connect to the power ground at the return terminal of the input capacitor. 4. if using a current sense resistor, the return path should be connected to pgnd and not agnd. volt?second clamp a volt?second clamp is an important safety feature in any forward converter, especially active clamp type where the duty ratio excursion can easily exceed 50%. a clamp helps to prevent magnetizing current runaway and transformer saturation in faulty situations. an external rc divider (r vsclamp ?c vsclamp ) from the input line generates the vsclamp ramp to control the volt?second limit of the converter. the slope of the ramp is proportional to the input voltage and controls the maximum on?time during a line voltage transition. the ramp prevents from exceeding the maximum volt?second of the transformer by clamping the duty ratio excursion during the transient input. as ncp1565 can be configured to operate in both voltage mode and peak current mode control, figures 53 and 54 respectively show the recommended clamp configuration for these operating modes. figure 53. the vsclamp configuration in voltage?mode control figure 54. the vsclamp configuration in peak current?mode control the pwm drive pulse terminates once the vsclamp ramp reaches v slimit , typically 1.5 v. the rc divider is selected such that the vsclamp ramp peak voltage reaches v slimit at the desired maximum volt?second limit. the vsclamp pin is pulled down by sw vsclamp at the end of every cycle and is held low until the next drive pulse. the volt?second limit depends on the transformer you have. assume the transformer specification allows a maximum volt?second product of 111.6 v? s for a 200 khz operation (62% duty ratio max at a 36 v input voltage). it means that maximum on?times at low and high line cannot respectively exceed: t on,maxll v? s max v in,min 111.6 36 3.1 s (eq. 6) t on,maxhl v? s v in,max 111.6 76 1.47 s (eq. 7) the rc network is thus dimensioned so that the ramp hits the 1.5?v limit in less than 1.47 s when the input voltage is 76 v or 3.1 s when the input is 36 v. let us select a normalized capacitor value of 1 nf for instance. in this case, if we consider a near?linear charging current (the series resistor is of high value), then the necessary current will be: i charge v limit c vsclamp t on,maxhl 1.5 1n 1.47 1.02 ma (eq. 8) a 1 ma current provides adequate noise immunity. in this case, r vsclamp is simply obtained by:
ncp1565 www. onsemi.com 25 r vsclamp t on,max c vsclamp ln 1
v slimit v in,max (eq. 9) 1.47 ln ln 1
1.5 76 73.74 k it is recommended to keep r vsclamp and c vsclamp close to the controller and away from high dv/dt signals such as drive outputs or swinging high?voltage nodes. c vsclamp must be connected to agnd for a reliable operation. comp input the pwm comparator modulates the duty ratio to regulate the output voltage. a signal proportional to the loop error signal is applied to this pin using an optocoupler. a voltage proportional to the error signal, v error , is internally generated and compared to a regulation ramp. the on?time terminates once the ramp exceeds the internal error voltage. in voltage?mode control the vsclamp ramp signal is used for regulation (see figure 53). in current mode control the sum of the current sense ramp and the voltage compensation ramp is used for regulation. the internal error voltage is generated by applying a current into the comp pin as shown in figure 55. the comp current is internally mirrored with a 10?to?1 ratio. the mirrored current pulls down on a 50 k pull?up resistor from v ref . 50k 400 1.35v vref pwm comp outm comp ramp figure 55. comp input architecture an almost constant voltage across the optocoupler is achieved when using a current?based feedback input. this results in a faster system response because duty ratio adjusts without the need to charge/discharge the large optocoupler parasitic capacitance. in the frequency domain, the optocoupler pole is moved to a higher frequency allowing the system to operate at a higher crossover frequency. the comp pin dynamic resistance is 400 . this resistance does not play a role in the loop gain but enters the picture if you plan to place a capacitor across the comp pin to ground. maximum duty ratio is achieved when the comp current is 0 a or when the pin is left open. a duty ratio of 0% is achieved when the comp current is approximately 850 a. frequency the oscillator frequency, f sw , is set by placing a resistor, r t , between the rt and agnd pins. the ncp1565 is optimized for operation between 200 khz and 1.5 mhz. equation 10 shows the relationship between f sw and r t . r t 1 f sw
20 ns 10 10 (eq. 10) r t should be placed directly across the rt and agnd pins. assuming a 200 khz switching frequency, then r t should be: r t 1 200k
20 ns 10 10 49.8 k (eq. 11) maximum duty ratio the maximum duty ratio of the oscillator is set by placing a resistor, r dlmt , between the dlmt and agnd pins. the adjustable duty ratio range is between 50% and 80%. the maximum duty ratio accuracy is 3%. the resistor that sets the maximum duty ratio depends on the timing resistance calculated in equation 10. it depends on the timing resistance but also on an overlap delay, t d1 . the overlap time (t d1 ) between outa and outm reduces the ef fective duty ratio of outm. please look in the electrical characteristics table to know what overlap value to use. r dlmt d max f sw t d1
20 ns r t f sw (eq. 12) assume our transformer specification states a maximum duty ratio of 62%. our circuit operates at a 200 khz frequency and the overlap time is set to 75 ns. we should place a resistance of the following value: r dlmt 0.62 200k 75n
20 ns 49.8k 200k (eq. 13) 31.4 k r dlmt should be placed directly across the dlmt and agnd pins. fault reporting and shutdown input the flt/sd pin reports the presence of a fault to an external supervisory circuitry. it also can be used to shutdown the controller if externally brought down. this pin has an open collector output with a 10 k internal pull?up resistor (r flt/sd ) connected to the 5 v reference. the flt/sd pin is internally pulled low (to indicate a fault) by an internal transistor, , when an overcurrent, short circuit, v cc(uvlo) , ovp, otp or low input voltage fault is detected. the pin is also pulled low when the controller is in restart mode. during the initialization sequence, the shutdown detection pin is released once v ref reaches its regulation level. the controller considered that the flt/sd pin is cleared from a fault when the pin voltage, v flt/sd , exceeds the enable threshold, v flt(enable) , typically 1.45 v, and v ss exceeds v ss(disable) , typically 0.5 v. the controller is disabled once v flt/sd , falls below the shutdown threshold,
ncp1565 www. onsemi.com 26 v fault , typically 1.25 v. while the controller is in shutdown state, v cc is hiccupping between 9.5/9.4 v typically and v ref is kept high. when the fl t/sd pin is brought low, the part activates the restart delay (res is cycled up and down 32 times) before a new restart is authorized when the flt/sd pin is released. restart mode the ncp1565 incorporates a restart timer to disable the controller for a certain amount of time and initiate a hiccup mode operation if a fault is detected. in short circuit operations, this technique limits the overall dissipated power. once the fault is gone, the controller automatically resumes operations. a restart event occurs if one of the following faults is detected: ? overcurrent fault (ocp) ? two consecutive short?circuit pulses (scp) ? overtemperature fault detected on otp pin ? internal thermal shutdown fault ? the pin has been externally pulled low please note that the pin is internally held low during the duration of the restart timer. the simplified architecture of the restart timer is shown in figure 56. figure 56. restart timer architecture a pull?down current source, i res(snk) , typically 5 a, holds the res pin at a low level when no faults are present. the restart timer sequentially charges and discharges 32 times the capacitor on the res pin, c res , between 2 v and 4 v to set the restart or hiccup duration. a fault triggers a restart or hiccup delay with the exception of an overcurrent fault. an overcurrent fault starts the shutdown delay timer before drive pulses are cut. a restart sequence initiates once the shutdown delay expires. the res pin combines two functions: the restart delay and the shutdown delay. as explained, the restart delay is made of 32 up/down cycles between 2/4 v on the res pin. the shutdown delay is actually the time taken by the res pin to charge from 0 to 1 v. this charge is initiated by the average input current reconstruction. when this internal averaged current exceeds 0.3 v, the capacitor on the res pin is charged by the 20 a source. if the overcurrent goes away, the capacitor slowly dischar ges by a 5 a pull?down current sink. if the fault comes back, the 5 a sink turns off and the 20 a is reactivated. when the capacitor voltage eventually reaches 1 v, all pulses are stopped and the part enters auto?recovery h iccup mode via the restart delay. figure 57 shows operating waveforms during an overload condition. the controller is disabled once v res exceeds 1 v.
ncp1565 www. onsemi.com 27 figure 57. overload condition operating waveforms hiccup is ensured by charging and discharging the capacitor connected to the res pin c res between 2 and 4 v. charge and discharge currents are equal to 5 a and respectively correspond to parameters i res(src2) and i res(snk) . the restart mode ends after 32 consecutive charge/discharge cycles. c res is then pulled low using an internal pull down transistor, sw res . the transistor is disabled once v res falls below the discharge level, v res(dis) , typically 100 mv. once c res is fully discharged a new startup sequence commences and soft?start is released. during the restart delay, the vcc pin is maintained by the controller operating the high?voltage current source in the dss mode: the voltage hiccups between 9.4 v and 9.5 v. figure 58. timing diagram exiting restart gate drive outputs the ncp1565 has two in?phase output drivers with an adaptive overlap delay (t d ). the main output, outm, can sink a minimum of 3 a and source a minimum of 2 a. the secondary output, outa, can sink a minimum of 1 a and source a minimum of 2 a. outm is configured to drive an n?channel mosfet as the main switch. outa is configured to drive a p?channel mosfet which source is grounded. outa is purposely sized smaller than outm because the active clamp mosfet only sees the magnetizing current in an active clamp forward topology. therefore, a smaller active clamp
ncp1565 www. onsemi.com 28 mosfet with less input capacitance is used compared to the main switch. also, on?losses associated with this p?channel have a beneficial damping effect on the l mag c clamp resonating network. once v cc reaches v cc(on) , the internal startup circuit is disabled and outa goes high to pre?charge the p?channel charge pump capacitor. outa goes low following outm after the overlap delay expires. outa remains high while the controller is disabled or until v cc falls below v cc(reset) . the outputs are biased directly from v cc and their high state voltage is approximately v cc . therefore, the auxiliary supply voltage should not exceed the maximum gate voltage of the main and active clamp mosfets. the inductance between the drivers and its load should be kept to a minimum to minimize current induced voltage spikes. this can be achieved by reducing the connection length between the drivers and their loads and using wide traces for connections. adaptive overlap time in an active clamp forward converter, there are two delays involved in the driving signals. both deal with zero v oltage switching (zvs) operations. when the main n?channel mosfet turns off, the magnetizing current finds an immediate path in the p?channel body diode. the conduction of this diode forces a low voltage across the drain?source terminals of the considered mosfet. once this condition is obtained, the p?channel can be turned on. this delay ensures zvs is present for the p?channel. to limit switching losses on the main n?channel mosfet, you also want to ensure quasi or full zvs operation. to meet this requirement, the p?channel will be turned off slightly before turning on the n?channel so that the drain?source voltage can swing down to ground or approach it: this is the second delay. a simplified block diagram and waveforms of an active clamp forward converter with a low side active clamp switch are shown in figure 59. driver outm drives the main switch where as outac drives the active clamp switch. overlap time between the drive signals is required to achieve zero or near zero volts switching (zvs) on the switches. figure 59. active?clamp forward topology outa leads outm during a low to high transition by a time duration given by t d1 . outa trails outm during a high to low transition by a time duration given by t d2 . figure 60 shows the overlap time delays between the outa and outm drive signals.
ncp1565 www. onsemi.com 29 figure 60. overlap time waveforms the overlap time is usually optimized for full?load efficiency. however, the optimum overlap time required to achieve zvs varies with line and load conditions. in light load, the magnetizing energy is reduced slowing down the drain voltage transitions. keeping the same overlap regardless of loading conditions can affect the converter?s efficiency along its operating range. ncp1565 adaptively adjusts the overlap times to optimize the system efficiency across operating conditions. the current sense information (representative of load) and the uvlo voltage (representative of input voltage) are used to adjust the overlap times. th e overlap times are essentially constant at mid to high load. in light load conditions, overlap times are inversely proportional to load and input voltage. the adaptive overlap time adjustment becomes active around 30% of the maximum load. the input voltage stops modulating the adaptive overlap timer once v uvlo exceeds approximately 3.5 v. a resistor, r dt , between the dt and agnd pins adjusts the overlap time. the minimum trailing delay is 20 ns. equations 14 and 15 show the relationship between overlap delays and r dt , the scaled?down input voltage and the current sense voltage. t d2 r dt 1.1 10 ?16 v uvlo 37.06k minimum v cs 2k , v uvlo 35k (eq. 14) t d1 t d2 0.66 (eq. 15) for our 200 khz dc?dc converter, we scaled down the input voltage by a ratio of 0.0365 before reaching the uvlo pin. for a 36 v input, we have 1.31 v on the uvlo pin. the dead?time resistance r dt has been selected to 65 k . if we plot equation 15 using mathcad ? as v cs varies from 0 to 0.45 v, we obtain figure 61 graph for three different input voltages (t 1ll for 36 v, t 1nl for 48 v and t 1hl for 76 v): 0 0.1 0.2 0.3 0.4 0 .5 figure 61. the dead time evolution with input voltage and the sensed current 4x10 ?7 2x10 ?7 0 t 1ll (v cs ) t 1nl (v cs ) t 1hl (v cs ) v cs (s) 3x10 ?7 1x10 ?7 t 1ll (v cs ) t 1nl (v cs ) t 1hl (v cs ) the trailing delay, t d2 , is 66% of the leading delay, t d1 . this allows the user to optimize the delay for the main switch optimum turn?on transition while ensuring the active clamp switch always exhibit zvs. the active clamp switch only sees the magnetizing current. therefore, having the body diode conduct for a small time period does not significantly impact the system efficiency. reference voltage a 5.0 v 2% reference is provided on the ref pin. it provides a minimum current of 12 ma. this reference can be used for biasing external circuitry. an external bypass capacitor is required for stability. the recommended minimum capacitance is 0.1 f. the reference is enabled once v uvlo exceeds v stby and v cc exceeds v cc(min) ,
ncp1565 www. onsemi.com 30 typically 6.5 v. it is disabled once v cc falls below v cc(reset) , typically 6.4 v. the reference pin incorporates an undervoltage detector. the reference is disabled if it falls below its undervoltage lockout threshold, v ref(uvlo) , typically 4.5 v. the reference undervoltage lockout has hysteresis, v ref(hys) , typically 200 mv. the controller is immediately disabled if a v ref undervoltage lockout fault is detected. a 1.5 s filter delay provides noise immunity. v ref is biased directly from v cc . therefore, if a load is applied to v cc while v ref is charging, chances exist to prevent the auxiliary voltage from properly building up, aborting the startup sequence. v cc and v ref capacitors should be sized such that the charging of v ref does not cause v cc to fall below v cc(reset) . otherwise, the reference will be disabled. if too much current is drawn from the ref pin, v cc will collapse. once v cc falls v cc(min) outa is forced high. once outm goes low, the controller is disabled resulting in a discharge of the soft?start capacitor. v ref and outa are disabled once v cc falls below v cc(reset) . once v ref is disabled, the overload condition is removed allowing v cc to charge back up. power dissipation the controller junction?to?ambient thermal resistance r ja depends on the available copper surface it is soldered upon. below are characterization data that link r j?a with copper surface and number of layers. 1 oz and 2 oz copper respectively correspond to 35 m and 70 m pcb copper thickness. cu area mm 1.0 oz 2.0 oz 100 131 115 125 122 107 150 115 101 200 105 93 300 93 82 400 85 75 500 79 69 600 74 66 qfn package 2 layer jedec eia/jesd 51.3 cu area mm 1.0 oz 2.0 oz 100 48 46 125 48 46 150 48 46 200 48 46 300 48 46 400 47 46 500 47 45 600 47 45 qfn package 4 layer jedec eia/jesd 51.7 35 m ja r copper area 70 m ja r temperature shutdown an internal thermal shutdown circuit monitors the junction temperature of the integrated circuit. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn , typically 165 c. the controller restarts once the ic temperature drops below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 20 c and v cc has charged to v cc(on) at least once while in thermal shutdown mode. a thermal shutdown fault is cleared if v cc drops below v cc(reset) , or if v uvlo falls below v stby by its hysteresis level. a power?up sequence commences at the next v cc(on) if all faults are removed. ordering information device package shipping ? NCP1565MNTXG qfn24 (pb?free) 4000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1565 www. onsemi.com 31 package dimensions case 485cw issue o 2.90 24x 0.32 24x 0.55 4.30 0.50 dimensions: millimeters 1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* pitch pkg outline dim min max millimeters d 4.00 bsc e 4.00 bsc a 0.80 1.00 b 0.21 0.31 e 0.50 bsc l1 --- 0.15 a3 0.20 ref a1 0.00 0.05 l 0.30 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. d2 e2 1 7 13 24 d2 2.10 2.30 e2 2.10 2.30 e l1 detail a l ?? ?? ?? 0.15 c pin one reference top view 2x 0.15 c a a1 (a3) 0.08 c 0.10 c c seating plane side view detail b bottom view b 24x 0.10 b 0.05 a c c note 3 detail a l 24x 4.30 2.90 constructions alternate constructions note 4 e/2 recommended on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1565/d mathcad is a registered trademark of parametric technology corporation. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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